1. Field of the Invention
This invention relates generally to a system for transferring data between a data processing module and a plurality of data processing modules. More particularly, the invention relates to a high-speed data communication system which transfers information between different digital processing modules on a shared parallel bus.
2. Description of the Related Art
For communication within a digital device, such as between a CPU (central processing unit), memory, peripherals, I/O (input/output) devices, or other data processors, a communication bus is often employed. As shown in FIG. 1, a communication bus is a set of shared electrical conductors for the exchange of digital words. In this manner, communication between devices is simplified, thereby obviating separate interconnections.
A communication bus typically contains a set of data lines, address lines for determining which device should transmit or receive, and control and strobe lines that specify the type of command is executing. The address and strobe lines communicate one-way from a central processing unit. Typically, all data lines are bidirectional.
Data lines are asserted by the CPU during the write instruction, and by the peripheral device during read. Both the CPU and peripheral device use three-state drivers for the data lines.
In a computer system where several data processing devices exchange data on a shared data bus, the two normal states of high and low voltage (representing the binary 1""s and 0""s) are implemented by an active voltage pullup. However, when several processing modules are exchanging data on a data bus, a third output state, open circuit, must be added so that another device located on the bus can drive the same line.
Three-state or open-collector drivers are used so that devices connected to the bus can disable their bus drivers, since only one device is asserting data onto the bus at a given time. Each bus system has a defined protocol for determining which device asserts data. A bus system is designed so that, at most, one device has its drivers enabled at one time with all other devices disabled (third state). A device knows to assert data onto the bus by recognizing its own address on the control lines. The device looks at the control lines and asserts data when it sees its particular address on the address lines and a read pulse. However, there must be some external logic ensuring that the three-state devices sharing the same lines do not talk at the same time or bus contention will result.
Bus control logic or a xe2x80x9cbus masterxe2x80x9d executes code for the protocol used to arbitrate control of the bus. The bus master may be part of a CPU or function independently. More importantly, control of the bus may be granted to another device. More complex bus systems permit other devices located on the bus to master the bus.
Data processing systems have processors which execute programmed instructions stored in a plurality of memory locations. As shown in FIG. 1, the processed data is transferred in and out of the system by using I/O devices onto a bus, interconnecting with other digital devices. A bus protocol, or handshaking rules delineate a predetermined series of steps to permit data exchange between the devices.
To move data on a shared bus, the data, recipient and moment of transmission must be specified. Therefore, data, address and a strobe line must be specified. There are as many data lines as there are bits in a word to enable a whole word to be transferred simultaneously. Data transfer is synchronized by pulses on additional strobe bus lines. The number of address lines determines the number of addressable devices.
Communication buses are either synchronous or asynchronous. In a synchronous bus, data is asserted onto or retrieved from the bus synchronously with strobing signals generated by the CPU or elsewhere in the system. However, the device sending the data does not know if the data was received. In an asynchronous bus, although handshaking between communicating devices assures the sending device that the data was received, the hardware and signaling complexity is increased.
In most high-speed, computationally intensive multichannel data processing applications, digital data must be moved very rapidly to or from another processing device. The transfer of data is performed between memory and a peripheral device via the bus without program intervention. This is also known as direct memory access (DMA). In DMA transfers, the device requests access to the bus via special bus request lines and the bus master arbitrates how the data is moved, (either in bytes, blocks or packets), prior to releasing the bus to the CPU.
A number of different types of bus communication systems and protocols are currently in use today to perform data transfer. As shown in the table of FIG. 2, various methods have been devised to manipulate data between processing devices. Data communication buses having powerful SDLC/HDLC (synchronous/high-level data link control) protocols exist, along with standardized parallel transmission such as small computer system interface (SCSI) and carrier-sense multiple-access/collision-detection (CSMA/CD)(Ethernet) networks. However, in specialized, high-speed applications, a simplified data communication bus is desired.
Accordingly, there exists a need for a simplified data processing system architecture to optimize data and message transfer between various processor modules residing on a data bus.
Method and apparatus for an arbitrated high speed control data bus system is provided which allows high speed communication between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO (first-in/first-out) queing, TTL CMOS (complimentary metal-oxide silicon) compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The present invention includes a parallel data bus with sharing bus masters residing on each processing module controlling the communication and data transfer protocols. The high-speed intermodule communication bus (HSB) provides between various microprocessor modules. The data bus is synchronous and completely bidirectional. Each processing module that communicates on the bus will have the described bus control architecture. The HSB comprises, in one embodiment, eight shared parallel data lines for the exchange of digital data, and two independent lines for arbitration and clock signals. The need for explicit bus request or grant signals is eliminated. The HSB can also be configured as a semi-redundant system, duplicating data lines while maintaining a single component level. The bus is driven by three-state gates with resistor pullups serving as terminators to minimize signal reflections.
To move data on the HSB, each processing module specifies the data, the recipient, and the moment when the data is valid. Only one message source, known as the bus master, is allowed to drive the bus at any given time. Since the data flow is bidirectional, the bus arbitration scheme establishes a protocol of rules to prevent collisions on the data lines when a given processing module microprocessor is executing instructions. The arbitration method depends on the detection of collisions present only on the arbitration bus and uses state machines on each data processing module to determine bus status. Additionally, the arbitration method is not daisy chained, allowing greater system flexibility. The state machines located on each processing module are the controlling interface between the microprocessor used within a given processing module and the HSB. The circuitry required for the interface is comprised of a transmit FIFO, receive FIFO, miscellaneous directional/bidirectional signal buffers and the software code for the state machines executed in an EPLD (erasable programmable logic device).
Objects and advantages of the system and method will become apparent to those skilled in the art after reading the detailed description of the preferred embodiment.